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author3gg <3gg@shellblade.net>2025-02-08 18:14:45 -0800
committer3gg <3gg@shellblade.net>2025-02-08 18:14:45 -0800
commit2dd1239ae661a1704c94501bbfc46afd4ca94863 (patch)
treeed441f19b2835807db9ed461f7d1b3db0aa024dc /src/uart.c
parent9bbddb13df34587d1e664b5f17d50778f6b48f7e (diff)
Comment.HEADmain
Diffstat (limited to 'src/uart.c')
-rw-r--r--src/uart.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/uart.c b/src/uart.c
index c5823e8..bb2a0ea 100644
--- a/src/uart.c
+++ b/src/uart.c
@@ -1,3 +1,7 @@
1/*
2References:
3 https://wiki.osdev.org/Raspberry_Pi_Bare_Bones
4*/
1#include <uart.h> 5#include <uart.h>
2 6
3#include <gpio.h> 7#include <gpio.h>
@@ -6,7 +10,8 @@
6enum 10enum
7{ 11{
8 // The base address for UART. 12 // The base address for UART.
9 UART0_BASE = (GPIO_BASE + 0x1000), // for raspi4 0xFE201000, raspi2 & 3 0x3F201000, and 0x20201000 for raspi1 13 // For raspi4 0xFE201000, raspi2 & 3 0x3F201000, and 0x20201000 for raspi1.
14 UART0_BASE = (GPIO_BASE + 0x1000),
10 // The offsets for reach register for the UART. 15 // The offsets for reach register for the UART.
11 UART0_DR = (UART0_BASE + 0x00), 16 UART0_DR = (UART0_BASE + 0x00),
12 UART0_RSRECR = (UART0_BASE + 0x04), 17 UART0_RSRECR = (UART0_BASE + 0x04),
@@ -48,13 +53,13 @@ void uart_init(int raspi) {
48 // Disable UART0. 53 // Disable UART0.
49 mmio_write(UART0_CR, 0x00000000); 54 mmio_write(UART0_CR, 0x00000000);
50 55
51 // Setup the GPIO pin 14 && 15. 56 // Set up GPIO pins 14 and 15.
52 57
53 // Disable pull up/down for all GPIO pins & delay for 150 cycles. 58 // Disable pull up/down for all GPIO pins.
54 mmio_write(GPPUD, 0x00000000); 59 mmio_write(GPPUD, 0x00000000);
55 delay(150); 60 delay(150);
56 61
57 // Disable pull up/down for pin 14,15 & delay for 150 cycles. 62 // Disable pull up/down for pins 14-15.
58 mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15)); 63 mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15));
59 delay(150); 64 delay(150);
60 65
@@ -90,7 +95,7 @@ void uart_init(int raspi) {
90 // Enable FIFO & 8 bit data transmission (1 stop bit, no parity). 95 // Enable FIFO & 8 bit data transmission (1 stop bit, no parity).
91 mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6)); 96 mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6));
92 97
93 // Mask all interrupts. 98 // Disable all interrupts.
94 mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) | 99 mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) |
95 (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10)); 100 (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10));
96 101